512-bit SRAM Schematic and Layout

For this project, I designed a 512-bit SRAM, with a word length of 32-bits. This project utilizes 2 separate 256-bit banks, each with 8 rows and 32 columns of 6-T SRAM cells. This SRAM was based on the TSMC 45nm process and includes pre-charge circuitry, a built-in row decoder, N-muxes for write-path column selection, P-muxes for read-path column selection, built-in write drivers and sense amps, and latches the output with a series of D-Flip-Flops.

10-Bit Multiply-Accumulator Schematic and Layout

In this project, I designed a 10-Bit Multiply-Accumulator circuit at the transistor level. The circuit takes 2 5-bit numbers as input, and will calculate their product. After the product is calculated, it will be accumulated in a D-Flip-Flop array, which also serves as the output for the circuit.


In this project, I collaborated with another student to develop a PONG clone on an FPGA. Our ultimate goal with this project was to create a simple, modular video game engine in Verilog.