512-bit SRAM Schematic and Layout

512-bit SRAM Schematic and Layout

Course: EE 577 – VLSI System Design

For this project, I designed a 512-bit SRAM, with a word length of 32-bits. This project utilizes 2 separate 256-bit banks, each with 8 rows and 32 columns of 6-T SRAM cells. This SRAM was based on the TSMC 45nm process and includes pre-charge circuitry, a built-in row decoder, N-muxes for write-path column selection, P-muxes for read-path column selection, built-in write drivers and sense amps, and latches the output with a series of D-Flip-Flops.

To create this project, I used Cadence Virtuoso to generate both a schematic and layout for the design. While designing the circuit, I incorporated transistor sizing to maintain correct setup and hold times, and to decrease overall delays.

The final 512-bit SRAM can theoretically achieve a speed of 2.9GHz, and has an overall area of 34.32um by 83.3um.




Functionality Tests