Projects
16-bit Execution Pipeline Schematic and Layout

16-bit Execution Pipeline Schematic and Layout

Course: EE 577 – VLSI System Design
Documentation: https://drive.google.com/file/d/15o5DwfA6FZSacqx44DMcjlooYvHdyRtE/view?usp=sharing

In this project, I worked with another student to designed a 16-bit execution pipeline, with support for Loads, Stores, Addition, Subtraction, and Multiplication.

In the design, there are 3 stages: Mem1, Execution, and Mem2. Mem1 acts like a register file, providing the Execution stage with 16-bit inputs. Mem2 is where the execution output is stored, and contains 32-bit values.

I specifically worked on the Execution stage, which incorporates a Booth multiplier and a Ripple-Carry Adder alongside control circuitry. My design incorporates Clock Gating on the multiplier, to reduce dynamic power leakage when no multiply instructions are in the pipeline. I also incorporated Domino Logic to reduce the delay on important control signals.

To create this project, I used Cadence Virtuoso to generate both a schematic and layout for the design. While designing the circuit, I incorporated transistor sizing to maintain correct setup and hold times, and to decrease overall delays.

The final execution pipeline can theoretically achieve a speed of 1.2GHz, with the bottleneck being memory access. The design has an overall area of 46.2um by 87.0um.

Images

Functionality

Schematics

Layouts