10-Bit Multiply-Accumulator Schematic and Layout

10-Bit Multiply-Accumulator Schematic and Layout

Course: EE 477 – MOS VLSI Circuit Design

In this project, I designed a 10-Bit Multiply-Accumulator circuit at the transistor level. The circuit takes 2 5-bit numbers as input, and will calculate their product. After the product is calculated, it will be accumulated in a D-Flip-Flop array, which also serves as the output for the circuit.

For this project, I used Cadence Virtuoso while creating both a schematic and layout for the design. While designing the circuit, I incorporated transistor sizing to maintain correct setup and hold times, and to decrease overall delays.

This project was completed in 3 phases. For each of these phases I created a schematic and a layout. The first phase was to build a 10-bit D-Flip-Flop (DFF), with asynchronous reset. The second phase was to build a 5-bit Array-Multiplication Unit (AMU), with a 10-bit output. The third and final phase was to create a 10-bit Kogge-Stone Adder (KSA). Once I was was done creating all three components, I connected them together to complete the MAC. The complete testing and design documentation for this circuit are included in the documentation link provided above.


Phase 1 – DFF

Phase 2 – AMU

Phase 3 – KSA

Final MAC